Sr. FPGA Engineer

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Electronics Design

3 - 6 Years

About Us

PierSight Space is building the world's first and largest constellation of Synthetic Aperture Radar and AIS satellites for persistent surveillance of the oceans. Our team has deep domain expertise with several live missions under our belt.

We've raised $6.6 million across pre-seed and seed rounds from Alpha Wave Ventures, Elevation Capital, Techstars, All In Capital, and angel investors. We were part of the Techstars Space Accelerator program which is in collaboration with NASA and US Space Force.

Founders

Gaurav Seth (CEO & Co-Founder) graduate from IIST and worked at ISRO for 9 years where he was instrumental in the design and execution of five interplanetary and earth observation missions. His achievements include the development of India's first airborne foliage penetration synthetic aperture radar and the SAR imaging payload aboard Chandrayaan-2.

Vinit Bansal (CTO & Co-Founder) is a graduate in Electronics from BITS-Pilani and has spent 9 years at National Instruments building and prototyping solutions for Space and Defence Industry. While working at National Instruments he worked closely with Indian Space Research Organisation and Ministry of Defence.

Founders

Role

3-6 years of hands-on experience in implementing designs on FPGA.
Strong expertise in RTL coding of complex designs using Verilog/SV.
Expertise in all aspects of FPGA design; constraint definition, synthesis, floor planning, P&R, Timing closure.
Early architectural/performance exploration through micro-architectural definition and design.
Optimize the design to meet power, performance, area and timing requirements.
Run unit level testing to deliver quality code to the Design Verification Team.
Create well written block level design documentation.
Write testbench and sequences in SystemVerilog.
Familiarity with lab equipment.
Familiarity with interface protocols (PCIE, Ethernet).
Knowledge of latest FPGA architectures and partitioning designs across multiple FPGAs.
Exposure to scripting languages.

3-6 years of hands-on experience in implementing designs on FPGA.
Strong expertise in RTL coding of complex designs using Verilog/SV.
Expertise in all aspects of FPGA design; constraint definition, synthesis, floor planning, P&R, Timing closure.
Early architectural/performance exploration through micro-architectural definition and design.
Optimize the design to meet power, performance, area and timing requirements.
Run unit level testing to deliver quality code to the Design Verification Team.
Create well written block level design documentation.
Write testbench and sequences in SystemVerilog.
Familiarity with lab equipment.
Familiarity with interface protocols (PCIE, Ethernet).
Knowledge of latest FPGA architectures and partitioning designs across multiple FPGAs.
Exposure to scripting languages.